Senior Staff Engineer
Hygon Austin R&D Center
I am a Senior Staff Engineer at Hygon Austin R&D Center (HARC).
Before joining HARC in Oct 2017, I spent 2.5 years at Samsung as a Performance Architect for the Samsung's premium ARM-based CPU that goes into high-end Exynos SOCs.
I received my PhD from University of Wisconsin-Madison working with Prof. Nam Sung Kim in 2015,
and my bachelor from Peking University in 2010.
Senior Staff Engineer at Hygon Austin R&D Center, Oct 2017 - Present
- Build performance study & analysis infrastructure (C++/Python) for server CPU architectural design
- build simpoint trace analysis framework, performance study flow, and statistics analysis tool
- conduct model vs. silicon correlation; improved correlated ratio from ~70% to 90%+
- Architected data prefetcher for next-gen CPU
- significant changes to AMD Zen’s design w/ centralized confidence/aggressiveness control
- designed a pointer engine to capture memory access patterns on complicated data structures
Senior Performance Architect at Samsung Austin R&D Center, Jun 2015 - Oct 2017
- Involved in 4 gens of Exynos mobile CPU design; filed 2 US patents; promoted after 1.5 years
- Made Exynos M4 score the highest in Geekbench v4 memory latency test among all competitors
- CPU architecture performance modeling (C++) and analysis
- develop a cycle-accurate performance simulator, w/ focus on memory system (LS/PF/MMU/L2)
- analyze workload characteristics & architectural performance bottlenecks
- Select of architected performance features:
- memory disambiguation, streaming detection & handling, memcpy optimization in Exynos M3
- spatially correlated prefetcher, cache conflict reduction technique in Exynos M4
Co-Op Engineer at AMD Research, Jan 2012 - Aug 2012
- Joint optimization of workload partitioning and dynamic voltage/frequency/core scaling (DVFS)
Ph.D. in Computer Architecture, University of Wisconsin-Madison, 2015
- Thesis: Heterogeneous processors and memory systems
- Published 6 first-author & 3 second-author papers; 3 US patents granted
- An integrated gem5+GPGPU-Sim simulator: http://cpu-gpu-sim.ece.wisc.edu
B.S. in MicroElectronics, Peking University, 2010
DUANG: Fast and lightweight page migration in asymmetric memory systems
Hao Wang, Jie Zhang, Sharmila Shridhar, Minwoo Lee, Myoungsoo Jung, Nam Sung Kim
IEEE Int. Symp. on High-Performance Computer Architecture (HPCA), Feb. 2016.
Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous Processors
Jaeyoung Jang, Hao Wang, Nam Sung Kim, Euijin Kwon, Jae Lee
IEEE Transactions on Parallel and Distributed Systems (TPDS), 2016
Alloy: Parallel-Serial Memory Channel Architecture for Single-Chip Heterogeneous Processor Systems
Hao Wang, Changjae Park, Gyungsu Byun, Jung Ho Ahn, Nam Sung Kim
IEEE Int. Symp. on High-Performance Computer Architecture (HPCA), Feb. 2015.
Memory Scheduling Toward High-Throughput Cooperative Heterogeneous Computing
Hao Wang, Ripudaman Singh, Michael Schulte, Nam Sung Kim
IEEE/ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), Aug. 2014.
Maximizing Throughput of Power/Thermal-constrained Processors by Balancing Power Consumption of Cores
Abhishek A. Sinkar, Hao Wang, Nam Sung Kim
IEEE Int. Symp. on Quality Electronics Design (ISQED), Mar. 2014.
Improving Platform Energy and Chip Area Trade-off in Near-Threshold Computing Environment
Hao Wang, Abhishek A. Sinkar, Nam Sung Kim
IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), Nov. 2013.
Improving Throughput of Many-core Processors Based on Unreliable Emerging Devices under Power Constraint
Hao Wang, Nam Sung Kim
IEEE Micro Magazine, vol. 33, no. 4, July-Aug. 2013.
Workload and Power Budget Partitioning for Single-Chip Heterogeneous Processors
Hao Wang, Vijay Sathish, Ripudaman Singh, Michael Schulte, Nam Sung Kim
IEEE/ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), Sep. 2012.
Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors
Abhishek A. Sinkar, Hao Wang, Nam Sung Kim
IEEE/ACM Design Automation and Test in European (DATE), Mar. 2012.
Asymmetric Issues of FinFET Device after Hot Carrier Injection and Impact on Digital and Analog Circuits
Chenyue Ma, Hao Wang, Xiufang Zhang, Frank He, Yadong He, Xing Zhang, Xinnan Lin
IEEE Int. Symp. on Quality Electronics Design (ISQED), Mar. 2010.
Program Committee Member
IEEE/ACM Journal Reviewer
Elsevier Journal Reviewer