Hao Wang

Senior Staff Engineer
Hygon Austin R&D Center


About Me

I am a Senior Staff Engineer at Hygon Austin R&D Center (HARC).
Before joining HARC in Oct 2017, I spent 2.5 years at Samsung as a Performance Architect for the Samsung's premium ARM-based CPU that goes into high-end Exynos SOCs.

I received my PhD from University of Wisconsin-Madison working with Prof. Nam Sung Kim in 2015, and my bachelor from Peking University in 2010.

Industry Experience


Eduction


Publication

  1. DUANG: Fast and lightweight page migration in asymmetric memory systems
    Hao Wang, Jie Zhang, Sharmila Shridhar, Minwoo Lee, Myoungsoo Jung, Nam Sung Kim
    IEEE Int. Symp. on High-Performance Computer Architecture (HPCA), Feb. 2016.
  2. Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous Processors
    Jaeyoung Jang, Hao Wang, Nam Sung Kim, Euijin Kwon, Jae Lee
    IEEE Transactions on Parallel and Distributed Systems (TPDS), 2016
  3. Alloy: Parallel-Serial Memory Channel Architecture for Single-Chip Heterogeneous Processor Systems
    Hao Wang, Changjae Park, Gyungsu Byun, Jung Ho Ahn, Nam Sung Kim
    IEEE Int. Symp. on High-Performance Computer Architecture (HPCA), Feb. 2015.
  4. Memory Scheduling Toward High-Throughput Cooperative Heterogeneous Computing
    Hao Wang, Ripudaman Singh, Michael Schulte, Nam Sung Kim
    IEEE/ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), Aug. 2014.
  5. Maximizing Throughput of Power/Thermal-constrained Processors by Balancing Power Consumption of Cores
    Abhishek A. Sinkar, Hao Wang, Nam Sung Kim
    IEEE Int. Symp. on Quality Electronics Design (ISQED), Mar. 2014.
  6. Improving Platform Energy and Chip Area Trade-off in Near-Threshold Computing Environment
    Hao Wang, Abhishek A. Sinkar, Nam Sung Kim
    IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), Nov. 2013.
  7. Improving Throughput of Many-core Processors Based on Unreliable Emerging Devices under Power Constraint
    Hao Wang, Nam Sung Kim
    IEEE Micro Magazine, vol. 33, no. 4, July-Aug. 2013.
  8. Workload and Power Budget Partitioning for Single-Chip Heterogeneous Processors
    Hao Wang, Vijay Sathish, Ripudaman Singh, Michael Schulte, Nam Sung Kim
    IEEE/ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), Sep. 2012.
  9. Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors
    Abhishek A. Sinkar, Hao Wang, Nam Sung Kim
    IEEE/ACM Design Automation and Test in European (DATE), Mar. 2012.
  10. Asymmetric Issues of FinFET Device after Hot Carrier Injection and Impact on Digital and Analog Circuits
    Chenyue Ma, Hao Wang, Xiufang Zhang, Frank He, Yadong He, Xing Zhang, Xinnan Lin
    IEEE Int. Symp. on Quality Electronics Design (ISQED), Mar. 2010.

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